This invention relates to gallium arsenide junction field effect transistors. More particularly this invention relates to complementary enhancement mode junction field effect transistors formed by planar processing techniques utilizing multiple ion implantations.
Gallium arsenide field effect transistors are a fairly recent development in semiconductor technology. Two different versions have emerged and have been developed more or less in parallel. One is the gallium arsenide Schottky-barrier FET or MESFET. The other is the enhancement mode junction field effect transistor (E-JFET) which is of primary interest herein. Either may be advantageously used for direct coupled logic (DCL) circuits. This E-JFET design leads to a reasonably low power integrated circuit technology with 100 microwatt per gate and a propagation delay time of 100 ps, i.e., delay-power product of 10 fJ when used in conjunction with a 5 K ohm resistive load. Although this low power dissipation per gate offers integration capability up to very large scale integration (VLSI) with 10,000 gates or more, for complex memory applications even lower power dissipations are demanded. With a resistive load memory cell using E-JFET drivers, a low power of 1-2 microwatts per cell has been achieved with a 256-bit static Random Access Memory (RAM) by using a 1 M ohm resistive load. This design path soon reaches a dead end due to subthreshold leakage currents which prevent lower power levels with resistive loads. Another low power 256-bit static RAM was designed with depletion mode (MESFET's) which utilizes a "power concentration" design approach for a 9 microwatts per cell power dissipation level.
For many important applications, ultra low-power circuits are necessary. One such application is for large scale memories used in space vehicles. In the case using n channel enhancement mode gallium arsenide JFET's and ion implanted resistive loads mentioned above, the best practical design resulted in a power dissipation of about two microwatts per cell which was several times higher than the design goal. Unfortunately, no existing prior art gallium arsenide MESFET or JFET technology can substantially improve upon this power dissipation level because of high subthreshold currents of the field effect transistors with only n channel device circuit design. Also the difficulty in obtaining a reasonable barrier height using GaAs MESFET technology prevents the creation of a useful complementary p channel device.